The present invention relates to a semiconductor integrated circuit device, and to a technique for laying out devices and interconnections employed in a dynamic RAM (Random Access Memory) wherein peripheral circuits comprised of random logic CIRCUITS and bonding pads are placed in a central portion of a semiconductor chip, for example.
An example of a dynamic RAM wherein bonding pads and their corresponding peripheral circuits are disposed in a central portion of a semiconductor chip is disclosed in U.S. Pat. No. 5,602,771 (Feb. 11, 1997). In the dynamic RAM disclosed in this patent, areas which constitute the peripheral circuits are provided crosswise in vertical and horizontal central portions of a memory chip. Memory arrays are laid out in areas divided into four parts by the cross-shaped areas.
A dynamic RAM comprises memory array portions formed by regular circuit patterns, and peripheral circuits each comprised of a random/logic circuit. Since the peripheral circuits are individually designed according to the storage capacity of each memory array or the type of operation mode, many design man-hours are spent to design such peripheral circuits and to lay them out. Therefore, the present inventors have sought a way of reducing the design man-hour of the random/logic circuit.
An object of the present invention is to provide a semiconductor integrated circuit device which is capable of implementing a rational layout of devices and interconnections. Another object of the present invention is to provide a semiconductor integrated circuit device which is capable of implementing a rational layout of circuit devices without degrading the performance of each circuit. The above, other objects and novel features of the present invention will become apparent from the description provided in the present specification and the accompanying drawings.
A summary of a typical aspects of the invention disclosed in the present application will be described in brief as follows. There is provided a semiconductor integrated circuit device wherein a plurality of unit regions or areas in which one or plural MOSFETs for implementing a specific logic circuit are formed, which unit regions or areas extend in a first direction, a first interconnection extending in the first direction is formed over the unit areas, a second interconnection extending in the first direction is formed along the unit areas and outside the unit areas, and each of the wiring dedicated areas is provided with a third interconnection extending in a second direction orthogonal to the first direction between the adjacent unit areas, a logic circuit formed in each unit area is constructed so as to have both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection through the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto as needed.